Principal Physical Layout Design Engineer/Sr. Principal Layout Design Engineer

Employer
Northrop Grumman
Location
Linthicum, MD
Posted
Nov 23, 2021
Closes
Dec 07, 2021
Ref
243222994
Industry
Engineering
Hours
Full Time
Requisition ID: R10001485Category: EngineeringLocation: Linthicum - MD, United States of AmericaCitizenship Required: United States CitizenshipClearance Type: SCITelecommute: No- Teleworking not available for this positionShift: 1st Shift (United States of America)Travel Required: Yes, 10% of the TimePositions Available: 2At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work "A cents € and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.The Northrop Grumman Mission Systems (NGMS) Advanced Processing Solutions Business pushes the boundaries of innovation, redefines the leading edge of exotic new technologies, and drives advances in the sciences. One of our most challenging new fields is Transformational Computing, which combines the unique properties of superconductivity and quantum mechanics to develop radical new energy-efficient computing systems. Our team is chartered with providing the skills to transform computing beyond Moore's Law, advancing development of computer architectures, processing/memory subsystems, and large scale high performance computing systems. You'll work in a fast-paced team environment alongside a broad array of scientists and engineers to make these processing solutions a reality and deliver remarkable new advantages to the warfighter.The Networked Information Solutions (NIS) Advanced Processing Solutions business is seeking a Physical Layout Design Engineer (T03-T04). The ideal candidate will have solid layout skills using Cadence Design suite of tools and the ability to script repetitive tasks in SKILL, Python, Linux Shell, etc. The development nature of our foundry activities will provide a willing candidate the opportunity to grow into an integral member of the Northrop Grumman design community.Possible responsibilities (but not limited to):Generate custom and semi-custom Virtuoso cell layoutsPlan and execute block level layouts, including initial floor planning and area estimations, taking in to account power and critical signal routing.Execute all required verification steps for a custom or semi-custom layout blockIntegrate custom and digital layout blocks with other features to produce a full chip designExecute full chip verification and chip finishing techniquesParticipate in reticle composition and tape out support activitiesCreate and document flows for future re-use and quality controlCreate custom layouts for Process Control Monitor (PCM) structures, reticle alignment marks, and physical measurement structures, with guidance from process development and photo lithography engineersThis position requires onsite support at our Linthicum, MD office.This position can be filled at a Principal level or a Sr. Principal Level. Qualifications for both are listed below:Basic Qualifications for a Principal Physical Layout Design Engineer:Bachelors Degree in STEM related field with 5 years of related experience; 3 years with MastersExperience using Cadence design suite of tools to perform full and semi-custom layoutThe ability to make minor schematic edits to support the layout effortThe ability to script within the Cadence environment using one of several compatible scripting languagesSolid knowledge of physical verification practices DRC, LVS, and PEXExperience with some of the following:Mixed-signal circuit design experience (Digital and Analog)Behavior modeling skills using Verilog-A or Verilog-AMSFull-chip functional/performance verification methods.Strong analysis and problem solving skillsExcellent verbal, written, and interpersonal communication skillsAble to obtain and maintain a DoD security clearance per business requirements.US CitizenshipPreferred Qualifications:Bachelor's degree (BSEE or other Engineering discipline) with 9 years of relevant experience (7 years with an MS and 4 years with a PhD).Knowledge of Cadence Virtuoso L/XL/EXL capabilities that enhance layout task efficiencyKnowledge of semiconductor device physics, process development, analog/mixed signal integrated circuit design, manufacturingExperience laying out digital standard cells and memory elements or characterizing standard cells and memoriesUnderstanding of Process Design Kit (PDK) Development (techfiles, verification rule files, p-cells, skill programing)Experience in superconducting Reciprocal Quantum Logic circuit design layout practicesCurrent Secret/TS SCI clearanceBasic Qualifications for a Sr. Principal Physical Layout Design Engineer:Bachelors Degree in STEM related field with 9 years of related experience; 7 years with Masters; 4 years with a PhDExperience using Cadence design suite of tools to perform full and semi-custom layoutThe ability to make minor schematic edits to support the layout effortThe ability to script within the Cadence environment using one of several compatible scripting languagesSolid knowledge of physical verification practices DRC, LVS, and PEXExperience with some of the following:Mixed-signal circuit design experience (Digital and Analog)Behavior modeling skills using Verilog-A or Verilog-AMSFull-chip functional/performance verification methods.Strong analysis and problem solving skillsExcellent verbal, written, and interpersonal communication skillsAble to obtain and maintain a DoD security clearance per business requirements.US CitizenshipPreferred Qualifications:Bachelor's degree (BSEE or other Engineering discipline) with 9 years of relevant experience (7 years with an MS and 4 years with a PhD).Knowledge of Cadence Virtuoso L/XL/EXL capabilities that enhance layout task efficiencyKnowledge of semiconductor device physics, process development, analog/mixed signal integrated circuit design, manufacturingExperience laying out digital standard cells and memory elements or characterizing standard cells and memoriesUnderstanding of Process Design Kit (PDK) Development (techfiles, verification rule files, p-cells, skill programing)Experience in superconducting Reciprocal Quantum Logic circuit design layout practicesCurrent Secret/TS SCI clearance"Salary Range: 96600 - 145000Salary Range 2: 119800 - 179600Employees may be eligible for a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit US Citizenship is required for most positions.

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